A timing generating circuit having a counter circuit structure shown in FIG. 6 is known. Specifically, this known timing generating circuit includes a counter circuit in which n stages of shift registers (S/R) 101-1 to 101-n are cascaded. As each CK input to the shift registers 101-1 to 101-n, a master clock MCK and its negative-phase clock XMCK are provided. When a start pulse ST is input to the first stage shift register 101-1, the shift registers 101-1 to 101-n perform shift operations in synchronism with the master clock MCK and XMCK to output shifted pulses as output pulses from each output terminal thereof.
If the above described timing generating circuit is formed including transistors having wide variations in their device properties and a high threshold Vth, for example, thin film transistors (TFTs) on an insulating substrate, such as a glass substrate, a matter of concern is that high (fast) frequencies in the master clock MCK and XMCK may cause problems in the counter operation (leave no operating margin). If the counter operates with such a high frequency, the power consumption in the timing generating circuit would increase. Further, a large layout area is needed since shift registers are required depending on the period of the output pulses and the TFTs have a larger process rule compared with the case where silicon is used.
FIG. 7 shows the circuit structure of another known timing generating circuit. This timing generating circuit may have an asynchronous counter circuit structure including three T-type flip-flops (hereinafter referred to as TFF) 102-1, 102-2, and 102-3 in which a lower-bit output from one TFF is a higher-bit input to another TFF. This known timing generating circuit, however, may malfunction due to delay variations in the TFFs 102-1, 102-2, and 102-3.
In view of the above mentioned problems, it is an object of the present invention to provide a timing generating circuit with low power consumption and small layout area even when transistors having wide variations in their device properties and a large process rule are used, a display apparatus including this timing generating circuit as one peripheral driving circuit, and a portable terminal including this display apparatus as a display output component.